I. Field of the Disclosure
The technology of the disclosure relates generally to metal interconnect structures formed in integrated circuits (ICs), and more particularly to forming vertical interconnect accesses (vias) in metal interconnect structures to provide interconnections between metal lines in the metal interconnect structures.
II. Background
Current semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), middle-of-line (MOL), and/or back-end-of-line (BEOL) processes. The FEOL processes may include wafer preparation, isolation, well formation, gate patterning, spacer, extension, and source/drain implantation, silicide formation, and the like. The MOL and/or BEOL processes may include gate contact formation and interconnection among differing layers of the ICs. The BEOL processes also include a series of wafer processing steps for interconnecting semiconductor devices created during the FEOL and MOL processes. Conventional BEOL processes in semiconductor fabrication employ Copper (Cu) interconnects and low dielectric constant (low-K) inter-layer dielectrics (ILDs) to reduce signal delay, cross talk, and power dissipation. These Cu interconnects can be made with a dual damascene process, and comprise vertical interconnect accesses (vias) and trench structures provided in the form of metal line structures. The metal line structures distribute signals within a given interconnect level, also referred to as a metal level or layer. Vias are interconnects that transmit signals between adjacent metal layers.
In this regard, FIG. 1A illustrates a top view of an interconnect structure 100 that can be provided in a semiconductor die 102. FIG. 1B illustrates a cross-sectional side view of the interconnect structure 100 in FIG. 1A along an A1-A1 line. The interconnect structure 100 employs a via VX to provide interconnections between adjacent upper and lower metal lines MX+1 and MX in a respective upper metal layer MLX+1 and lower metal layer MLX. The notation ‘X+1’ denotes that the upper metal layer MLX+1 and upper metal lines MX+1 are disposed directly above and adjacent to the lower metal layer MLX and lower metal lines MX in this example. The via VX may be fabricated using a dual damascene process wherein an ILD 104 and the upper metal layer MLX+1 are first deposited and patterned using lithography. The upper metal line MX+1 and via VX are created as a result of etching and metal deposition. Thus, the via VX is aligned to the upper metal layer MLX+1 of the interconnect structure 100 as part of the fabrication process, as shown in FIGS. 1A and 1B. The via VX is offset from the lower metal line MX, which increases via resistance of the via VX. The via VX being offset from the lower metal line MX also causes the via VX to be located a via-metal short distance S away from the adjacent lower metal line MX(N). However, the ILD 104 between the lower metal lines MX, MX(N) provides isolation between the lower metal line MX(N) and the via VX to avoid an electrical short (i.e., a via-metal short) between the lower metal lines MX, MX(N). The alignment of the via VX to the lower metal line MX will vary based on variations in the fabrication process.
If a metal pitch P in the semiconductor die 102 in FIGS. 1A and 1B was scaled down in size, a metal pitch P of the interconnect structure 100 would also be reduced as a result. However, as the metal pitch P of the interconnect structure 100 is reduced, the misalignment of the via Vx with the lower metal line MX is likely to increase, thus resulting in an increased via VX resistance. Increased via Vx resistance causes increased signal delay between the metal lines MX, MX+1. Further, reducing the metal pitch P of the interconnect structure 100 may further reduce the via-metal short distance S between the via VX and the adjacent metal line MX(N). The shorter via-metal short distance S may cause the ILD 104 to incur breakdown, creating an electrical short between the lower metal lines MX, MX(N). This may be particularly true for a sub-30 nanometer (nm) metal pitch P of the interconnect structure 100 in FIGS. 1A and 1B. However, there is a desire and need for continued scaling down of device sizes in semiconductor devices, while still providing for an interconnect structure with lower interconnect resistance and sufficient isolation between vias and metal lines to avoid via-metal shorts.